US 11,862,248 B2
Semiconductor storage device
Mai Shimizu, Kamakura Kanagawa (JP); Koji Kato, Yokohama Kanagawa (JP); Yoshihiko Kamata, Yokohama Kanagawa (JP); and Mario Sako, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jan. 30, 2023, as Appl. No. 18/161,274.
Application 18/161,274 is a continuation of application No. 17/591,216, filed on Feb. 2, 2022, granted, now 11,600,328.
Application 17/591,216 is a continuation of application No. 16/952,858, filed on Nov. 19, 2020, granted, now 11,276,466, issued on Mar. 15, 2022.
Application 16/952,858 is a continuation of application No. 16/283,239, filed on Feb. 22, 2019, granted, now 10,872,668, issued on Dec. 22, 2020.
Application 16/283,239 is a continuation of application No. 15/695,470, filed on Sep. 5, 2017, granted, now 10,255,977, issued on Apr. 9, 2019.
Claims priority of application No. 2017-056335 (JP), filed on Mar. 22, 2017.
Prior Publication US 2023/0178152 A1, Jun. 8, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/24 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3427 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor storage device, comprising:
a first memory cell electrically connected to a first bit line and a first word line;
a second memory cell electrically connected to a second bit line and the first word line; and
a first circuit configured to supply voltages to the first word line, wherein
during a reading operation to read a page of memory cells including the first memory cell and the second memory cell, while the first memory cell is selected as a read target during a first time period, the first circuit supplies:
a first voltage to the first word line in an initial state during the first time period,
a second voltage that is greater than the first voltage to the first word line after supplying the first voltage,
a third voltage that is less than the second voltage to the first word line directly after supplying the second voltage; and
during the reading operation to read the page of memory cells including the first memory cell and the second memory cell, while the second memory cell is selected as the read target during a second time period that is different from the first time period, the first circuit supplies:
the first voltage to the first word line in an initial state during the second time period,
the second voltage to the first word line after supplying the first voltage,
a fourth voltage that is less than the third voltage and greater than the first voltage to the first word line directly after supplying the second voltage, and
the third voltage to the first word line directly after supplying the fourth voltage.