CPC G11C 11/4085 (2013.01) [G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 11/4087 (2013.01); G11C 11/4094 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a first transistor coupled to a first word line at a first node;
a second transistor coupled to a second word line different from the first word line at a second node, wherein a control terminal of the first transistor is coupled to a control terminal of the second transistor; and
a third transistor coupled between a ground and a third node which is coupled to each of the first node and the second node,
wherein in a layout view, each of the first transistor and the second transistor has a first length along a direction, and
the first transistor, the third transistor and second transistor are arranged in order along the direction.
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