CPC G11C 11/2273 (2013.01) [G11C 5/06 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2275 (2013.01)] | 20 Claims |
1. A memory device comprising:
a substrate;
a ferroelectric field effect transistor disposed on the substrate;
a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor;
a selection word line disposed at a side of the first channel;
a first gate dielectric layer disposed between the first channel and the selection word line; and
a cell word line disposed on top of the first channel.
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