US 11,862,220 B2
Memory device
Minjun Lee, Seoul (KR); Yongseok Kim, Suwon-si (KR); Hyuncheol Kim, Seoul (KR); Jongman Park, Hwaseong-si (KR); Dongsoo Woo, Seoul (KR); and Kyunghwan Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 9, 2022, as Appl. No. 17/836,228.
Claims priority of application No. 10-2021-0135934 (KR), filed on Oct. 13, 2021.
Prior Publication US 2023/0112070 A1, Apr. 13, 2023
Int. Cl. G11C 11/22 (2006.01); G11C 5/06 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 5/06 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2275 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a substrate;
a ferroelectric field effect transistor disposed on the substrate;
a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor;
a selection word line disposed at a side of the first channel;
a first gate dielectric layer disposed between the first channel and the selection word line; and
a cell word line disposed on top of the first channel.