US 11,862,217 B2
Device, sensor node, access controller, data transfer method, and processing method in microcontroller
Masanori Natsui, Sendai (JP); Daisuke Suzuki, Sendai (JP); Akira Tamakoshi, Sendai (JP); Takahiro Hanyu, Sendai (JP); Tetsuo Endoh, Sendai (JP); and Hideo Ohno, Sendai (JP)
Assigned to TOHOKU UNIVERSITY, Sendai (JP)
Appl. No. 17/430,000
Filed by TOHOKU UNIVERSITY, Sendai (JP)
PCT Filed Feb. 15, 2020, PCT No. PCT/JP2020/005928
§ 371(c)(1), (2) Date Feb. 1, 2022,
PCT Pub. No. WO2020/166725, PCT Pub. Date Aug. 20, 2020.
Claims priority of application No. 2019-026134 (JP), filed on Feb. 16, 2019.
Prior Publication US 2022/0157361 A1, May 19, 2022
Int. Cl. G11C 11/16 (2006.01); G06F 17/14 (2006.01)
CPC G11C 11/1673 (2013.01) [G06F 17/142 (2013.01); G11C 11/1653 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A device, comprising:
an MRAM configured to include multiple memory cells separated into multiple regions including selection transistors and MTJs;
a nonvolatile CPU configured to include a nonvolatile memory;
a nonvolatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU in parallel; and
a power-gating controller configured to control power supply to each memory cell in the MRAM, the nonvolatile CPU, and the nonvolatile FPGA-ACC,
wherein the device is a single-chip microcomputer having the MRAM, the nonvolatile CPU, the nonvolatile FPGA-ACC, and the power-gating controller.