US 11,862,216 B2
Shift register and driving method therefor, gate driver circuit, and display apparatus
Zhu Wang, Beijing (CN); Ling Shi, Beijing (CN); Yipeng Chen, Beijing (CN); Hui Lu, Beijing (CN); Zhenglong Yan, Beijing (CN); Changchang Liu, Beijing (CN); and Ke Liu, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/927,535
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Oct. 27, 2021, PCT No. PCT/CN2021/126754
§ 371(c)(1), (2) Date Nov. 23, 2022,
PCT Pub. No. WO2022/227453, PCT Pub. Date Nov. 3, 2022.
Claims priority of application No. 202110476525.2 (CN), filed on Apr. 29, 2021.
Prior Publication US 2023/0207031 A1, Jun. 29, 2023
Int. Cl. G11C 19/02 (2006.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G11C 19/28 (2013.01) [G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register, comprising:
an input circuit coupled to a signal input terminal, a first voltage signal terminal and a first node; and the input circuit being configured to transmit, under control of an input signal from the signal input terminal, a first voltage signal from the first voltage signal terminal to the first node;
a first control circuit coupled to the first node, a first clock signal terminal, a second voltage signal terminal and a second node; and the first control circuit being configured to transmit, under control of a first clock signal from the first clock signal terminal and a voltage at the first node, a second voltage signal from the second voltage signal terminal to the second node;
a second control circuit coupled to the second node, a second clock signal terminal and a third node; and the second control circuit being configured to transmit, under control of a voltage at the second node, a second clock signal from the second clock signal terminal to the third node; and
an output circuit coupled to the third node, the first voltage signal terminal and a scan signal output terminal; and the output circuit being configured to transmit, under control of a voltage at the third node, the first voltage signal from the first voltage signal terminal to the scan signal output terminal.