CPC G09G 3/346 (2013.01) [G09G 5/395 (2013.01); G09G 5/399 (2013.01); H03M 7/30 (2013.01); G09G 2310/08 (2013.01); G09G 2340/02 (2013.01); G09G 2370/00 (2013.01)] | 20 Claims |
1. A circuit comprising:
a first data element, wherein the first data element is a first portion of a bus;
a second data element, wherein the second data element is a second portion of the bus;
a first buffer having a first buffer input and a first buffer output, the first buffer output coupled to the first data element, the first buffer adapted to be coupled to a first clock;
a second buffer having a second buffer input and a second buffer output, the second buffer output coupled to the second data element and the second buffer input coupled to the first buffer output, the second buffer adapted to be coupled to a second clock;
logic circuits coupled to the first data element and to the second data element; and
a parallel register coupled to the logic circuits.
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