US 11,861,781 B2
Graphics processing units with power management and latency reduction
Sreekanth Godey, Santa Clara, CA (US); Ashkan Hosseinzadeh Namin, Markham (CA); Seunghun Jin, Suwon-Si (KR); and Teik-Chung Tan, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US); ATI TECHNOLOGIES ULC, Markham (CA); and SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 28, 2020, as Appl. No. 17/134,744.
Prior Publication US 2022/0207813 A1, Jun. 30, 2022
Int. Cl. G06F 1/3228 (2019.01); G06T 15/00 (2011.01); G06F 1/3212 (2019.01); G06F 9/50 (2006.01); G06F 1/3215 (2019.01); G06F 9/30 (2018.01)
CPC G06T 15/005 (2013.01) [G06F 1/3212 (2013.01); G06F 1/3215 (2013.01); G06F 1/3228 (2013.01); G06F 9/30098 (2013.01); G06F 9/5011 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method comprising:
in response to rendering, by a graphics processing unit (GPU), a first image frame and prior to receiving an indication of a second image frame for rendering:
storing GPU state information on retention hardware of the GPU,
transitioning the retention hardware into a retention state, and
transitioning the GPU into a low-power state; and
transitioning the GPU into an active state in response to receiving the indication of the second image frame for rendering.