CPC G06J 1/00 (2013.01) [G06F 17/16 (2013.01)] | 20 Claims |
1. A device comprising:
a first processing core comprising a resistive memory array to perform an analog computation;
a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions; and
a controller to selectively apply input data to the first processing core and the digital processing core.
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