US 11,861,429 B2
Resistive and digital processing cores
John Paul Strachan, Milpitas, CA (US); Dejan S. Milojicic, Milpitas, CA (US); Martin Foltin, Ft. Collins (CO); Sai Rahul Chalamalasetti, Milpitas, CA (US); and Amit S. Sharma, Milpitas, CA (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Appl. No. 17/049,031
Filed by Hewlett Packard Enterprise Development LP, Houston, TX (US)
PCT Filed Apr. 30, 2018, PCT No. PCT/US2018/030125
§ 371(c)(1), (2) Date Oct. 20, 2020,
PCT Pub. No. WO2019/212466, PCT Pub. Date Nov. 7, 2019.
Prior Publication US 2021/0240945 A1, Aug. 5, 2021
Int. Cl. G06J 1/00 (2006.01); G06F 17/16 (2006.01)
CPC G06J 1/00 (2013.01) [G06F 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first processing core comprising a resistive memory array to perform an analog computation;
a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions; and
a controller to selectively apply input data to the first processing core and the digital processing core.