US 11,861,365 B2
Macro-op fusion
Krste Asanovic, Berkeley, CA (US); and Andrew Waterman, Berkeley, CA (US)
Assigned to SiFive, Inc., San Mateo, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on May 3, 2021, as Appl. No. 17/306,373.
Application 17/306,373 is a continuation of application No. 16/215,328, filed on Dec. 10, 2018, granted, now 10,996,952.
Prior Publication US 2021/0255859 A1, Aug. 19, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3017 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3844 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit for executing instructions comprising:
one or more execution resource circuits configured to execute micro-ops to support an instruction set including macro-ops,
an instruction decode buffer configured to store macro-ops fetched from memory, and
an instruction decoder circuit configured to:
detect a sequence of macro-ops stored in the instruction decode buffer, the sequence of macro-ops including a control-flow macro-op followed by one or more additional macro-ops;
determine a micro-op that is equivalent to the detected sequence of macro-ops; and
forward the micro-op to at least one of the one or more execution resource circuits for execution.