CPC G06F 9/3017 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3844 (2013.01)] | 20 Claims |
1. An integrated circuit for executing instructions comprising:
one or more execution resource circuits configured to execute micro-ops to support an instruction set including macro-ops,
an instruction decode buffer configured to store macro-ops fetched from memory, and
an instruction decoder circuit configured to:
detect a sequence of macro-ops stored in the instruction decode buffer, the sequence of macro-ops including a control-flow macro-op followed by one or more additional macro-ops;
determine a micro-op that is equivalent to the detected sequence of macro-ops; and
forward the micro-op to at least one of the one or more execution resource circuits for execution.
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