CPC G06F 8/65 (2013.01) [G06F 9/4403 (2013.01)] | 7 Claims |
1. A method of operating a memory controller including a plurality of cores and a buffer memory, the method comprising:
suspending an execution of running code in a core arbitrarily selected from among the plurality of cores;
allocating an target address different from an address where the running code is stored in a memory of the selected core;
loading a boot loader image for firmware update from the buffer memory into the target address;
receiving a new firmware image from a host in response to the boot loader image executed in the selected core; and
updating a firmware image stored in a memory of each of the plurality of cores with the new firmware image.
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