CPC G06F 5/012 (2013.01) [G06F 7/49947 (2013.01); G06F 2207/3844 (2013.01)] | 11 Claims |
1. A computer-implemented method comprising:
dividing a fraction of a floating point result into a first portion and a second portion;
outputting a first normalizer result based on the first portion during a first designated computer clock cycle;
storing, via a latch having a bit width size that can retain a first segment of the first portion, the first segment of the first portion during the first designated computer clock cycle;
outputting a first rounder result based on the first normalizer result during the first designated computer clock cycle;
outputting a second normalizer result based on the second portion during a second designated computer clock cycle; and
outputting a second rounder result based on the second normalizer result and the first segment during the second designated computer clock cycle.
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