US 11,861,281 B2
Computer-implemented method and computing system for designing integrated circuit by considering timing delay
Jong-pil Lee, Suwon-si (KR); Bong-il Park, Seongnam-si (KR); Moon-su Kim, Gimpo-si (KR); and Sun-ik Heo, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 17, 2022, as Appl. No. 17/966,993.
Application 17/156,738 is a division of application No. 15/862,296, filed on Jan. 4, 2018, granted, now 10,902,168, issued on Jan. 26, 2021.
Application 17/966,993 is a continuation of application No. 17/156,738, filed on Jan. 25, 2021, granted, now 11,475,195.
Claims priority of application No. 10-2017-0055660 (KR), filed on Apr. 28, 2017.
Prior Publication US 2023/0037826 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/3323 (2020.01); G06F 30/392 (2020.01); G06F 30/3312 (2020.01); G06F 30/398 (2020.01); G06F 30/394 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3323 (2020.01) [G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable storage medium that stores computer program code which, when executed by at least one processor, causes the at least one processor to execute a plurality of tools for designing an integrated circuit (IC), the plurality of tools comprising:
a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net; and
a timing analysis tool that:
calculates a wire delay with respect to the wire corresponding to the net, based on the physical information,
updates the wire delay based on process variation of the wire, and
calculates a timing slack by using the updated wire delay,
wherein the physical information includes at least one of length information of the wire, width information of the wire, area information of the wire, space information of the wire, and shielding information of the wire, and
wherein the process variation includes one or more of a resistance variation, a capacitance variation, and a via variation due to a manufacturing process of the wire.