CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0683 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory array comprising a plurality of planes;
a primary plane driver circuit comprising components to support a plurality of types of memory access operations on any of the plurality of planes; and
a plurality of secondary plane driver circuits, each comprising components to support a single type of memory access operation on an associated one of the plurality of planes concurrently with a memory access operation being performed by the primary plane driver circuit on a different one of the plurality of planes.
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