US 11,861,236 B2
Asymmetric plane driver circuits in a multi-plane memory device
Kalyan Chakravarthy C. Kavalipurapu, Hyderabad (IN); Chang H. Siau, Saratoga, CA (US); and Shigekazu Yamada, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 11, 2022, as Appl. No. 17/742,294.
Application 17/742,294 is a continuation of application No. 16/947,525, filed on Aug. 5, 2020, granted, now 11,354,067.
Prior Publication US 2022/0276806 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0683 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of planes;
a primary plane driver circuit comprising components to support a plurality of types of memory access operations on any of the plurality of planes; and
a plurality of secondary plane driver circuits, each comprising components to support a single type of memory access operation on an associated one of the plurality of planes concurrently with a memory access operation being performed by the primary plane driver circuit on a different one of the plurality of planes.