US 11,861,228 B2
Memory status command aggregation
Karl D. Schuh, Santa Cruz, CA (US); Ali Mohammadzadeh, Mountain View, CA (US); Dheeraj Srinivasan, San Jose, CA (US); Daniel J. Hubbard, Boise, ID (US); and Luca Bert, San Jose, CA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 29, 2021, as Appl. No. 17/514,267.
Claims priority of provisional application 63/230,500, filed on Aug. 6, 2021.
Prior Publication US 2023/0043418 A1, Feb. 9, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
aggregating a plurality of memory status commands, wherein the plurality of memory status commands includes a first memory status command and a second memory status command, the first and second memory status commands differing from one another;
assigning each command of the plurality of memory status commands a corresponding bit on a memory interface; and
sending the plurality of memory status commands in parallel as an aggregate status command to one or more memory components via the memory interface.