US 11,861,226 B2
Semiconductor memory device
Akio Sugahara, Yokohama (JP); Zhao Lu, Ebina (JP); Takehisa Kurosawa, Yokohama (JP); and Yuji Nagai, Sagamihara (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 2, 2021, as Appl. No. 17/464,791.
Claims priority of application No. 2021-057290 (JP), filed on Mar. 30, 2021.
Prior Publication US 2022/0317932 A1, Oct. 6, 2022
Int. Cl. G11C 7/00 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first pad configured to receive a first signal;
a second pad configured to receive a second signal;
a third pad configured to receive a third signal;
a first memory cell array comprising a plurality of first memory strings, the plurality of first memory strings each comprising a plurality of first memory cell transistors;
a first sense amplifier connected to the first memory cell array;
a first data register connected to the first sense amplifier and configured to store data read from the first memory cell array; and
a control circuit configured to execute an operation targeting the first memory cell array, wherein
the first pad is provided in plurality,
in a first mode, a command set instructing the operation is inputted via the first pads, and
in a second mode, the command set is inputted via the second pad and the third pad.