US 11,861,212 B2
Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence
Tsu-Han Lu, Hsinchu (TW); and Hsiao-Chang Yen, Hsinchu County (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Feb. 24, 2022, as Appl. No. 17/679,120.
Prior Publication US 2023/0280929 A1, Sep. 7, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, comprising:
an input/output (110) circuit, coupled to the flash memory device through the specific communication interface, for sending commands and data between the flash memory device and a processor; and
the processor, coupled to the I/O circuit, for controlling the I/O circuit sending a set-feature signal to the flash memory device to enable, disable, or configure an access operation of the flash memory device, to make the flash memory device perform the access operation to control the flash memory device generating second address information associated with a second plane of the flash memory device according to a first address information of a first plane of the flash memory device, and then selecting multiple data units at the first plane and the second plane based on the first address information and the second address information in response to an access command or a specific indication command so as to perform the access operation upon the multiple data units at the first plane and the second plane;
wherein the set-feature signal comprises a set-feature command and a feature information which is associated with the access operation; the access operation is a copy back read operation, an erase operation, or a write operation; and, the feature information comprises a parameter data; when the parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is enabled and configured as a sequential mode which is arranged to sequentially access data units of the different planes of the flash memory device according to serial numbers of the different planes in response to the access command or the specific indication command sent from the flash memory controller.