US 11,861,211 B2
System which provides plural processes in a host with asynchronous access to plural portions of the memory of another host
Gal Shalom, Givat Avni (IL); Adi Horowitz, Tel Aviv (IL); Omri Kahalon, Yehud (IL); Liran Liss, Atzmon (IL); Aviad Yehezkel, Yoqneam Illit (IL); and Rabie Loulou, Nazareth (IL)
Assigned to MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Dec. 6, 2021, as Appl. No. 17/543,334.
Prior Publication US 2023/0176769 A1, Jun. 8, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 9/54 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01); G06F 9/544 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus that implements an API (application programming interface) that is operative in conjunction with a bridge chip, a first host and a second host, wherein the first and second hosts have first and second memories, respectively, and wherein the bridge chip connects the first and second memories, the apparatus comprising:
a processor that provides:
key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers;
access control functionality to provide at least one computer process P1 performed by the first host with access, via the bridge chip, to at least one local memory buffer M2 residing in the second memory after the access control functionality first validates that said at least one computer process P1 has a key identifier which has been registered via the key identifier registration functionality, and wherein the access control functionality also prevents at least one computer process P2, which is performed by the first host and which has not registered a key identifier via the key identifier registration functionality, from accessing the at least one local memory buffer M2 via the bridge chip,
an additional key identifier registration functionality; and
an additional access control functionality, which provides at least one computer process P3 performed by the second host with access via the bridge chip to at least one local memory buffer M1 residing in the first memory after the additional access control functionality first validates that said at least one computer process P3 has a key identifier which has been registered via the additional key identifier registration functionality, and wherein the additional access control functionality also prevents at least one computer process P4, which is performed by the second host and which has not registered a key identifier via the additional key identifier registration functionality, from accessing the at least one local memory buffer M1 via the bridge chip.