US 11,861,195 B2
TLC data programming with hybrid parity
Sergey Anatolievich Gorobets, Edinburgh (GB); Alan D. Bennett, Edinburgh (GB); Liam Parker, Edinburgh (GB); Yuval Shohet, Acton, MA (US); and Michelle Martin, Westford, MA (US)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Mar. 15, 2021, as Appl. No. 17/202,163.
Prior Publication US 2022/0291838 A1, Sep. 15, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0626 (2013.01); G06F 3/0673 (2013.01); G06F 11/1004 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive host data from a host device;
generate first exclusive or (XOR) parity data for the host data;
encode the host data and the first XOR parity data with an encoder;
write the encoded host data and the first XOR parity data to a first memory superblock;
decode valid data and the first XOR parity data written to the first memory superblock, wherein the valid data corresponds with the host data that has not become obsolete when located in the first memory superblock;
generate second XOR parity data for the decoded valid data;
re-encode the decoded valid data and the second XOR parity data with the encoder; and
write the re-encoded valid data and the second XOR parity data to a second memory superblock, wherein the re-encoded second XOR parity data has a size that is less than the size of the first XOR parity data.