US 11,861,010 B2
Extensible device hosted root of trust architecture for integrated circuits
Sonal Santan, San Jose, CA (US); Yu Liu, Newark, CA (US); Yenpang Lin, Campbell, CA (US); Lizhi Hou, Santa Clara, CA (US); Cheng Zhen, San Jose, CA (US); and Yidong Zhang, Fremont, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Feb. 14, 2022, as Appl. No. 17/651,030.
Prior Publication US 2023/0259627 A1, Aug. 17, 2023
Int. Cl. G06F 21/64 (2013.01); G06F 21/71 (2013.01); G06F 21/57 (2013.01); G06F 13/16 (2006.01)
CPC G06F 21/572 (2013.01) [G06F 13/1642 (2013.01); G06F 13/1663 (2013.01); G06F 21/64 (2013.01); G06F 21/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a queue configured to receive host commands from a host computer via a communication link with the host computer; and
a processor coupled to the queue and configured to operate as a Root of Trust (RoT) for the integrated circuit through execution of firmware, wherein the processor, responsive to executing the firmware, is configured to perform validation of the host commands read from the queue and selectively execute the host commands in response to a successful validation of the host commands on a per host command basis;
wherein the host commands are executable by the processor to manage functions of the integrated circuit; and
wherein the queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.