US 11,861,000 B2
Memory system
Joon-Woo Choi, Busan (KR); and Jeong-Tae Hwang, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Apr. 7, 2020, as Appl. No. 16/842,483.
Claims priority of application No. 10-2019-0096200 (KR), filed on Aug. 7, 2019.
Prior Publication US 2021/0042407 A1, Feb. 11, 2021
Int. Cl. G06F 21/00 (2013.01); G06F 21/55 (2013.01)
CPC G06F 21/554 (2013.01) 6 Claims
OG exemplary drawing
 
1. A memory system comprising:
a first memory and a second memory that share common addresses received from a memory controller,
wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and
the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and
the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.