US 11,860,775 B2
Method and apparatus for programming data into flash memory incorporating with dedicated acceleration hardware
Shen-Ting Chiu, Miaoli County (TW)
Assigned to Silicon Motion, Inc., Zhubei (TW)
Filed by Silicon Motion, Inc., Zhubei (TW)
Filed on Aug. 2, 2022, as Appl. No. 17/879,180.
Claims priority of provisional application 63/249,702, filed on Sep. 29, 2021.
Claims priority of application No. 202210339320.4 (CN), filed on Apr. 1, 2022.
Prior Publication US 2023/0094268 A1, Mar. 30, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0831 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 3/061 (2013.01); G06F 3/0658 (2013.01); G06F 3/0689 (2013.01); G06F 12/0831 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for programming data into flash memory, performed in a flash controller, wherein the flash controller comprises a processing unit, a routing engine and an accelerator, the method comprising:
receiving, by the routing engine, operating settings and a front-end parameter set of a first data-programming transaction from the processing unit, wherein the operating settings indicate whether each of a front-end processing stage, a mid-end processing stage and a back-end processing stage is required to be activated;
driving, by the routing engine, a host interface (I/F) to obtain first data from a host side and store the first data in a first designated address of a random access memory (RAM) through a shared bus architecture according to the front-end parameter set when determining that the front-end processing stage needs to be activated for the first data-programming transaction according to the operation settings;
receiving, by the accelerator, the operation settings, a mid-end parameter set and a back-end parameter set from the processing unit;
driving, by the accelerator, a redundant array of independent disks (RAID) engine to obtain second data from a second designated address of the RAM through the shared bus architecture, and encrypt the second data or generate a parity-page data in terms of multiple pages of the second data according to the mid-end parameter set when receiving an activation message for the first data-programming transaction from the routing engine and determining that the mid-end processing stage needs to be activated for the first data-programming transaction according to the operation settings; and
driving, by the accelerator, a data access engine to obtain third data from a third designated address of the RAM through the shared bus architecture and program the third data into a designated address of a flash module when determining that the mid-end processing stage does not need to be activated for the first data-programming transaction according to the operation settings or the mid-end processing stage has been completed, and the back-end processing stage needs to be activated for the first data-programming transaction according to the operation settings.