US 11,860,751 B1
Deterministic data latency in serializer/deserializer-based design for test systems
Abhijeet Samudra, Sunnyvale, CA (US); Ajay Nagarandal, Sunnyvale, CA (US); Anubhav Sinha, Hyderabad (IN); Luis M. Cruz, Maia (PT); Milin Kaushik Raijada, Hyderabad (IN); Ramalingam Kolisetti, Hyderabad (IN); Naresh Thakur, Hyderabad (IN); Saransh Nagaich, Bangalore (IN); and Jatin Verma, Hyderabad (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jun. 17, 2022, as Appl. No. 17/843,231.
Claims priority of provisional application 63/212,517, filed on Jun. 18, 2021.
Int. Cl. G06F 11/00 (2006.01); G06F 11/263 (2006.01); G06F 11/22 (2006.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01)
CPC G06F 11/263 (2013.01) [G01R 31/317 (2013.01); G01R 31/3183 (2013.01); G01R 31/318307 (2013.01); G06F 11/2268 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, from an automated test equipment (ATE), test packets comprising test pattern data to test a design under test (DUT), wherein the test packets are received over a serializer/deserializer (SERDES) connection between the ATE and the DUT;
applying, by a circuit in the DUT, the test pattern data to the DUT using a set of scan chains and obtaining test response data corresponding to the test pattern data;
receiving, by the circuit in the DUT, the test response data at irregular time intervals; and
sending, by the circuit in the DUT, response packets comprising a portion of the test response data to the ATE at regular time intervals, wherein the response packets are sent to the ATE over the SERDES connection.