US 11,860,745 B2
Redundant edge hardware
Eric Bruno, Shirley, NY (US); and Dragan Savic, Toronto (CA)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Apr. 5, 2022, as Appl. No. 17/713,304.
Prior Publication US 2023/0315590 A1, Oct. 5, 2023
Int. Cl. G06F 11/20 (2006.01); G06F 11/14 (2006.01); G06F 11/36 (2006.01)
CPC G06F 11/2002 (2013.01) [G06F 11/1438 (2013.01); G06F 11/3688 (2013.01); G06F 11/3692 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
executing a testing operation on a plurality of redundant components of an edge device;
identifying, based, at least in part, on the testing operation, at least one redundant component of the plurality of redundant components as having an operational issue;
deactivating the at least one redundant component in response to the identifying;
utilizing one or more remaining redundant components of the plurality of redundant components in one or more operations following the testing operation;
executing a plurality of respective workloads on the plurality of redundant components, wherein the executing of the plurality of respective workloads yields a plurality of respective outputs;
timestamping the plurality of respective outputs with respective times, wherein the executing of the testing operation is performed at a time after the respective times;
invalidating at least one output of the plurality of respective outputs corresponding to the at least one redundant component and timestamped with a corresponding one of the respective times; and
re-executing at least one workload of the plurality of respective workloads corresponding to the at least one invalidated output on a remaining redundant component of the one or more remaining redundant components to produce at least one new output in place of the at least one invalidated output;
wherein the method is performed by at least one processing device comprising a processor coupled to a memory.