US 11,860,733 B2
Memory matched low density parity check coding schemes
Eran Sharon, Rishon Lezion (IL); Ran Zamir, Ramat Gan (IL); David Avraham, Even Yehuda (IL); and Idan Alrod, Herzeliya (IL)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Dec. 8, 2021, as Appl. No. 17/545,051.
Prior Publication US 2023/0176947 A1, Jun. 8, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); H03M 13/11 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/1048 (2013.01); H03M 13/1114 (2013.01); H03M 13/1125 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a memory interface configured to interface with a non-volatile memory; and
a controller configured to: receive a plurality of data pages associated with a write command, the plurality of data pages to be stored in the non-volatile memory, wherein the plurality of data pages is N data pages,
transform the plurality of data pages associated with the write command into a plurality of transformed data pages, wherein the plurality of transformed data pages is 2N−1 data pages,
determine a plurality of parity bits based on the plurality of transformed data pages, and
store the plurality of data pages and the plurality of parity bits in the non-volatile memory.