CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/1048 (2013.01); H03M 13/1114 (2013.01); H03M 13/1125 (2013.01)] | 20 Claims |
1. A memory controller, comprising:
a memory interface configured to interface with a non-volatile memory; and
a controller configured to: receive a plurality of data pages associated with a write command, the plurality of data pages to be stored in the non-volatile memory, wherein the plurality of data pages is N data pages,
transform the plurality of data pages associated with the write command into a plurality of transformed data pages, wherein the plurality of transformed data pages is 2N−1 data pages,
determine a plurality of parity bits based on the plurality of transformed data pages, and
store the plurality of data pages and the plurality of parity bits in the non-volatile memory.
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