CPC G06F 1/08 (2013.01) [G06F 1/12 (2013.01); H03K 5/00006 (2013.01); H03K 2005/00058 (2013.01)] | 20 Claims |
1. A clock oscillator control circuit comprising:
a signal processor including an output;
logic circuitry comprising:
a first inverter including an input and an output;
a second inverter including an input coupled to the output of the signal processor, wherein the second inverter further includes an output;
a first logic gate including a first input coupled to the output of the signal processor, wherein the first logic gate further includes a second input coupled to the output of the first inverter, and wherein the first logic gate further includes an output; and
a second logic gate including a first input coupled to the output of the second inverter, wherein the second logic gate further includes a second input coupled to the input of the first inverter, and wherein the second logic gate further includes an output; and
a set-reset latch comprising:
a set input configured to the output of the first logic gate; and
a reset input configured to the output of the second logic gate.
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