US 11,860,672 B2
Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD
Sompong Paul Olarig, Pleasanton, CA (US); Fred Worley, San Jose, CA (US); and Oscar P. Pinto, San Jose, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 28, 2019, as Appl. No. 16/260,087.
Application 16/260,087 is a continuation in part of application No. 16/226,629, filed on Dec. 19, 2018, granted, now 10,838,885.
Application 16/226,629 is a continuation of application No. 16/207,080, filed on Nov. 30, 2018, granted, now 10,635,609.
Claims priority of provisional application 62/745,261, filed on Oct. 12, 2018.
Claims priority of provisional application 62/638,040, filed on Mar. 2, 2018.
Prior Publication US 2019/0310957 A1, Oct. 10, 2019
Int. Cl. G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); H03M 13/15 (2006.01); G06F 3/06 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 3/061 (2013.01); G06F 3/065 (2013.01); G06F 3/0683 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); H03M 13/154 (2013.01); G06F 2213/0026 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A system, comprising:
a first Non-Volatile Memory Express (NVMe) Solid State Drive (SSD);
a second NVMe SSD;
a Field Programmable Gate Array (FPGA), the FPGA implementing one or more functions supporting the first NVMe SSD, the functions comprising at least one of data acceleration, data deduplication, data integrity, data encryption, and data compression, and including a Peripheral Component Interconnect Express (PCIe) switch, the PCIe switch including a processing circuit configured to direct an NVMe storage command, sent to the system, to the FPGA;
wherein the PCIe switch communicates with the FPGA and is connected to the first NVMe SSD, and
wherein the PCIe switch receives the NVMe storage command sent to the system and delivers the NVME storage command to the FPGA based at least in part on the processing circuit.