US 11,860,659 B2
Low drop-out (LDO) linear regulator
Joongho Choi, Seongnam-si (KR); Minsu Park, Seoul (KR); Jiteck Jung, Seongnam-si (KR); Seungwoo Shin, Seoul (KR); Chankyu Bae, Goyang-si (KR); Kibaek Kwon, Seoul (KR); Myunsik Kim, Seoul (KR); Jiwon Son, Cheongju-si (KR); and Heain Kim, Guri-si (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 27, 2021, as Appl. No. 17/562,277.
Claims priority of application No. 10-2020-0186682 (KR), filed on Dec. 29, 2020.
Prior Publication US 2022/0206521 A1, Jun. 30, 2022
Int. Cl. G05F 1/575 (2006.01)
CPC G05F 1/575 (2013.01) 10 Claims
OG exemplary drawing
 
1. A low drop-out (LDO) linear regulator, comprising:
a pass transistor coupled between an input terminal and an output terminal;
an error amplifier suitable for amplifying and outputting a difference between a feedback voltage corresponding to an output voltage of the output terminal and a predetermined reference voltage;
a buffer including an input terminal which is coupled to an output node of the error amplifier and an output terminal which is coupled to a gate of the pass transistor;
a first compensation circuit suitable for driving an equivalent resistance of the output node of the error amplifier to be in inverse proportion to a load current; and
a second compensation circuit suitable for driving an equivalent resistance of an output node of the buffer to be in inverse proportion to the load current, wherein second compensation circuit includes a transistor which is coupled in parallel to a bias current source of the buffer so as to supply a current proportional to a square of the load current to the bias current source of the buffer.