US 11,860,228 B2
Integrated circuit chip testing interface with reduced signal wires
Albert Shih-Huai Lin, Mountain View, CA (US); Niravkumar Patel, San Jose, CA (US); Amitava Majumdar, San Jose, CA (US); and Jane Wang Sowards, Fremont, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on May 11, 2022, as Appl. No. 17/742,363.
Prior Publication US 2023/0366929 A1, Nov. 16, 2023
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/318555 (2013.01) [G01R 31/31727 (2013.01); G01R 31/318572 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip device comprising:
a first IC chip comprising:
first testing circuitry configured to receive a mode select signal, a clock signal, and encoded signals, the first testing circuitry comprising:
finite state machine (FSM) circuitry configured to determine an instruction based on the mode select signal and the clock signal;
decoder circuitry configured to decode the encoded signals to generate a decoded signal; and
control circuitry configured to generate a control signal from the instruction and the decoded signal, wherein the control signal indicates a test to be performed by the first testing circuitry.