US 11,860,227 B2
Machine learning delay estimation for emulation systems
Yanhua Yi, Cupertino, CA (US); Yu Yang, Shanghai (CN); Jiajun Fan, Shanghai (CN); Vinod Kumar Nakkala, San Jose, CA (US); Vijay Sundaresan, Milpitas, CA (US); and Jianfeng Huang, Shanghai (CN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/548,317.
Claims priority of provisional application 63/124,332, filed on Dec. 11, 2020.
Prior Publication US 2022/0187367 A1, Jun. 16, 2022
Int. Cl. G06F 9/455 (2018.01); G01R 31/3183 (2006.01); G06F 30/3308 (2020.01); G06F 11/26 (2006.01)
CPC G01R 31/318321 (2013.01) [G01R 31/318328 (2013.01); G01R 31/318357 (2013.01); G06F 11/261 (2013.01); G06F 30/3308 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer readable medium comprising stored instructions for delay estimation, wherein the stored instructions, when executed by a processor, cause the processor to:
receive a plurality of logic blocks of a design under test (DUT);
identify a combinatorial path based on the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
generate a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
apply a pre-trained machine learning delay model to the feature vector to determine a wire delay of the combinatorial path, the pre-trained machine learning delay model trained using (1) values of the one or more orthogonal features representing the characteristics of a plurality of combinatorial paths, and (2) measured wire delays of the plurality of combinatorial paths;
generate a timing graph based on the wire delay of the combinatorial path; and
provide the timing graph to a compiler to perform placement and routing of the DUT.