CPC G01R 31/318321 (2013.01) [G01R 31/318328 (2013.01); G01R 31/318357 (2013.01); G06F 11/261 (2013.01); G06F 30/3308 (2020.01)] | 20 Claims |
1. A non-transitory computer readable medium comprising stored instructions for delay estimation, wherein the stored instructions, when executed by a processor, cause the processor to:
receive a plurality of logic blocks of a design under test (DUT);
identify a combinatorial path based on the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
generate a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
apply a pre-trained machine learning delay model to the feature vector to determine a wire delay of the combinatorial path, the pre-trained machine learning delay model trained using (1) values of the one or more orthogonal features representing the characteristics of a plurality of combinatorial paths, and (2) measured wire delays of the plurality of combinatorial paths;
generate a timing graph based on the wire delay of the combinatorial path; and
provide the timing graph to a compiler to perform placement and routing of the DUT.
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