US 11,860,116 B2
Semiconductor devices including crack sensor
Jong Su Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 8, 2022, as Appl. No. 17/689,489.
Claims priority of application No. 10-2021-0136148 (KR), filed on Oct. 13, 2021.
Prior Publication US 2023/0110075 A1, Apr. 13, 2023
Int. Cl. H01L 23/522 (2006.01); G01N 27/20 (2006.01); H01L 21/66 (2006.01); H01L 49/02 (2006.01)
CPC G01N 27/20 (2013.01) [H01L 22/34 (2013.01); H01L 23/5228 (2013.01); H01L 28/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate including chip regions and a scribe lane region;
a target layer disposed on the substrate; and
a crack sensor for detecting a crack generated in the target layer,
wherein the crack sensor includes:
a first conductive pattern positioned at a bottom surface of the target layer;
a second conductive pattern positioned on a top surface of the target layer, the top surface being opposite to the bottom surface of the target layer;
a plurality of resistors substantially penetrating the target layer, the plurality of resistors connected in parallel to each other through the first conductive pattern and the second conductive pattern, wherein each of the plurality of resistors is disposed sequentially away from the chip region; and
a first node and a second node connected to the first conductive pattern and the second conductive patterns, respectively.
 
17. A semiconductor device comprising:
a target layer disposed on a substrate; and
a crack sensor for detecting a crack generated in the target layer,
wherein the crack sensor includes:
a first conductive pattern positioned at a bottom surface of the target layer;
a second conductive pattern positioned on a top surface of the target layer, the top surface being opposite to the bottom surface of the target layer;
a plurality of resistors substantially penetrating the target layer, the plurality of resistors connected in parallel to each other through the first conductive pattern and the second conductive pattern; and
a first node and a second node connected to the first conductive pattern and the second conductive pattern, respectively.