US 10,170,340 B2
Semiconductor structure
Po Chun Lin, Changhua (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, Taoyuan (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Dec. 21, 2017, as Appl. No. 15/851,595.
Application 15/851,595 is a division of application No. 15/333,933, filed on Oct. 25, 2016.
Prior Publication US 2018/0122653 A1, May 3, 2018
Int. Cl. H01L 23/28 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01)
CPC H01L 21/565 (2013.01) [H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/28 (2013.01); H01L 23/31 (2013.01); H01L 23/3107 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a chip disposed over the substrate; and
a molding disposed over the substrate and surrounding the chip at a molding temperature,
wherein the substrate includes a curved configuration at a side opposite to the chip, and the molding includes a reduced size which compensates a warpage of the curved configuration of the substrate at the molding temperature, so that the warpage of the substrate is convex or about zero at the molding temperature or 10° C. more or less than the molding temperature.